The present invention relates to an ESDI interface control circuit.
Recently an interface has been adopted for use in data processing systems, which interface is named ESDI, acronym for Enhanced Small Device Interface.
This interface is of a serial type, makes use of a small number of leads of the transfer of binary information and is well suited for connecting controllers to disk units.
The ESDI interface comprises six leads.
A first lead COMMAND is used to transfer in serial mode from the controller to a peripheral unit a command consisting of 16 bits plus an odd parity check bit.
A second lead, CONF. STATUS is used to transfer in serial mode from a peripheral unit to the controller information relating to the status and the features of the peripheral unit. This information consists of 16 bits plus an odd parity check bit.
The information exchange occurs through an interlocked dialogue conducted over two control leads, TRANSFER REQUEST and ACKNOWLEDGE.
The controller always leads the dialogue by sending a command in case peripheral status information is to be received.
The interface-protocol logic is inverted relative to the electrical level of the signals: in other words a signal is asserted or true when at electrical level 0 volts and deasserted or false when at positive elctrical level.
In order to control the interface dialogue, the controller puts a first bit of information on lead COMMAND and asserts a signal REQ on lead TRANSFER REQUEST (hereinafter TR).
On receipt of REQ the peripheral unit answers by asserting a signal ACK on lead ACKNOWLEDGE.
On receipt of ACK the controller deasserts (negates) signal REQ and the information bit present on lead COMMAND is replaced with a new information bit.
On receipt of signal REQ at logical level 0, the peripheral unit resets signal ACK to logical level 0.
On receipt of signal ACK at level 1, the controller asserts again signal REQ, and so on until the full transfer of the 17 bits of information has occurred.
If the command information which has been sent requires the receiving of status information, once the 17 bits have been forwarded to the peripheral unit, the controller asserts again signal REQ.
In response to such request, the peripheral unit puts a first information bit on lead CONF. STATUS, then asserts signal ACK.
On receipt of signal ACK asserted, the controller loads the information bit in a register and removes or negates signal REQ.
On receipt of signal REQ false the peripheral unit negates signal ACK.
On receipt of signal ACK at level 1, the controller asserts again signal REQ to request a second status information bit and so on, untill the 17th bit is received, in which case the controller does not assert signal REQ any more in order to terminate the transfer operation.
The other two interface leads, named CC (Command complete) and ATT (Attention) are used by the peripheral unit; the first (CC) to notify the controller that the peripheral unit is ready to receive a command, because the previous one has been executed, and particularly, if the command was a request to receive status information, to notify that the transfer has occurred; the second (ATT) to notify the controller that within the peripheral unit a status change has occurred and the controller is invited to perform a status read dialogue (preceded by the related command).
On lead CC, signal COMM is asserted if at electrical level 0 and rises to a positive electrical level when a command information begins to be received. It drops to zero once the received command has been executed.
On lead ATT, the signal is normally at positive electrical level and drops to 0 when the signal is asserted.
The preceding description of the ESDI interface communication protocol is useful to understand the scope and the advantages of the invention: A control circuit for ESDI interface must comprise means for sending and receiving information in serial form, timing means for timing the transfer operation and counting means for counting the number of bits sent and received.
Although the applicant does not know of any document describing such a control circuit for an ESDI interface, it is conceptually possible to devise, as an obvious design choice, a control circuit comprising a shift register for serialization of a data output from controller, a shift register for serially receiving and parallel reading of serial data input, a counter for counting the bits transmitted and received and timing circuits for timing the dialogue.
An embodiment of this kind would be complex and expensive.
The ESDI interface control circuit overcomes these disadvantages, which is the object of the present invention. The resulting control circuit is very simple and inexpensive.
According to the invention a single shift register is used to serialize a parallel command information to be transmitted, bit by bit, and to obtain in parallel form status information which is received in serial form.
Moreover the same shift register is loaded with control information at a predetermined electrical level so that the status of the shift register defines the number of transmitted or received bits and enables stopping of the transfer process without need of counters.
The shift register is activated by two firmware commands, which preset the status of two control flip flops, as a function of the operations to be performed and provide control signals to a timing logic. The timing logic is triggered by one of the firmware commands, to generate signal REQ and a clock signal for the shift register, is maintained in active state by signals ACK received from the peripheral unit and is stopped by the control information loaded in the shift register. This control information further resets one of the two control flip flops.